Semiconductor memory pipeline buffer

ABSTRACT

A high capacity, fast access dynamic random access memory is provided. Furthermore, a pipelined write method can be realized at each array block by affixing a latch between the sense amplifier and write data line for each column. In this manner, a data write phase can occur simultaneously with the pre-read phase of the following address. Using this method, the effective access speed to the array block can be increased, yielding a fast access cache memory.

RELATED APPLICATION

The present application is a continuation of U.S. patent applicationSer. No. 10/774,586, filed Feb. 10, 2004, which claims priority toJapanese Patent Application No. 2003-205615 filed on Aug. 4, 2003, theentire disclosure of the above-referenced parent application beingincorporated herein by reference.

COPYRIGHT NOTICE

A portion of the disclosure of this patent document contains materialwhich is subject to copyright protection. The copyright owner has noobjection to the facsimile reproduction by anyone of the patent documentor the patent disclosure, as it appears in the Patent and TrademarkOffice patent file or records, but otherwise reserves all copyrightrights whatsoever.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to semiconductor memories and,more particularly, to a series of array structures, arrangements, andactivation schemes for high density, fast access semiconductor memoriesthat have a separate read and write data line and that exhibitdestructive write behavior.

2. Discussion of Background

In conventional microprocessors, a cache memory module is fabricated onthe same semiconductor die as the processing logic in order toaccommodate rapid data and instruction storage and retrieval.Semiconductor memories for on-chip cache applications are typicallycomprised of six-transistor static random access memory (6T SRAM) orone-transistor one-capacitor dynamic random access memory (1T-1C DRAM).The 6T cell is the more common solution since the access speed is fasterand design and production costs are low since the memory can befabricated next to the logic with a minimal addition in processingsteps. However, as cache memory capacity requirements greatly increaseto accommodate for multimedia processing, the large cell size of the 6TSRAM leads to a large area, high cost cache memory solution.

A 1T-1C DRAM memory cell can be used as a semiconductor memory when highbit density is required. This technology has several drawbacks and facesserious complications as device dimensions are scaled smaller. Notably,since the DRAM cell has no internal gain, a high capacitance element(˜30 fF) must be fabricated in each cell to store a charge large enoughto be reliably detected. Therefore, complex capacitor structures andexpensive materials must be used to build a device with adequatecapacitance, which leads to expensive fabrication and incompatibilitieswith standard logic processes.

Inexpensive gain cell technologies (for example, three transistor (3T)memory cell technologies) with bit densities much larger than SRAM havebeen proposed to provide high-density cache memories. However, theseoften fail to be used in products because of a slower access time thanSRAM. In a conventional destructive write dual data line gain cellmemory, the output of the sense amplifier of the read data line signalis directly connected to the write data line. A write access proceeds asfollows. Data is first read from all cells in the selected row byactivating the read word line and discriminating the data with a senseamplifier. New data presented to the bank is written over the old dataonly in the selected columns. A data write phase then occurs in whichthe data in the sense amplifiers is applied to the write data line andthe write word line is activated, transferring the new data to theselected cells. In this manner, the write cycle time is the summation ofthe read and write phases. This long read then write cycle is a seriousdetriment to gain cell solutions, especially those with a longer writephase.

For solving the above problems, a 3T memory cell technology written inJP10-134565 proposes. FIG. 3 shows a part of the FIG. 1 of JP10-134565.The 3T memory cell of FIG. 3 separates write word line and uses ANDlogic of write word line signal WWL and column select signal WY forselecting the write word line. In this way the write operation canbecome a non-destruction operation because the number of memory cellsselected by the write word line is equal to the number of data writtento memory cells. Therefore it does not need to read the data from thememory cells selected by write word line and high speed write operationcan be realized.

Although it is efficient to use this technology in writing a lot of bitsof data, it is difficult to adopt this technology in writing small bitsof data, for example 8 bit data. The reason of this is because it needsto separate the write word line every 8 bit, the region of AND circuitfor selecting the write word line and wiring of the column select signalincreases. Therefore the feature of 3T memory cell that is high densityis damaged.

SUMMARY OF THE INVENTION

Broadly speaking, the present invention fills these needs by providing ahigh capacity, fast access dynamic random access memory. It should beappreciated that the present invention can be implemented in numerousways, including as a process, an apparatus, a system, a device or amethod. Several inventive embodiments of the present invention aredescribed below.

According to at least one preferred embodiment of the present invention,a memory is provided comprising a plurality of memory cells, eachcontaining a gain cell structure. Furthermore, the present inventioncomprises a method of data access in which data is read from the cellarray and written to the cell array simultaneously. In this manner, theread and write phases of the destructive write cycle of a gain cell canbe overlapped, or pipelined, for consecutive accesses. This leads to anoverall increase in the effective access speed of the cache memory. Inaddition, the circuitry to enable this method is located at each memorybank and requires minimal external control, presenting a solution to theslow access cycle of a gain cell memory with negligible area andprocessing overhead.

The data write method presented in at least one of the preferredembodiments is distinct from the conventional case due to the insertionof a data latch between the sense amplifier and the write data line. Awrite cycle proceeds similar to the conventional case by firstconducting a read phase in which the old row data is read into the senseamplifiers. As the signals develop, the new data replaces the old datain the selected columns and the combined data is stored in the latchesconnected to the sense amplifier. The write phase occurs when the datastored in the latches is presented to the write data line and the writeword line is activated, transferring the new data to the cells. Animportant point of the present invention is that as the write data lineis activated and data is written to the cells in the write phase, theread phase of the following read-or write-cycle can proceedsimultaneously. This is because the data stored in the latch can beapplied to the write data line while the sense amplifier is used todiscriminate the data on the read data line. Once the write phase iscomplete, the data from the next accessed row stored in the senseamplifier is stored in the latch and the cycle can repeat. This pipelinewrite presents an effective access time to the CPU the same length asthe read or write phase, whichever is longer, greatly reducing theaccess time of the cache memory.

Another aspect of the present invention is the structure of the rowdecoding logic. Since two word lines can be active simultaneously, astandard row decoder and word line driver configuration cannot be used.This invention utilizes a latch at the output of the decoder circuit tostore the value of the signal presented to the read word line driver.The output of the latch is connected to the write word line driver andthis word line driver is activated when the data is written to the row.The write word line can be activated while the subsequent address isdecoded and presented to the read word line for the following access. Inthis manner, a single address decoder can be used for two simultaneousword line activations with only a minimal addition of circuitry.

Presented in at least one embodiment is the memory block structure inwhich two separate memory mats share a sense amplifier and buffercircuit. In this configuration, the write data of two memory cell arrayscan be stored in a single row of buffers in order to yield a memory thatoccupies a reduced area on the silicon die.

Also presented in at least one embodiment is the multi-buffer method. Inthis case, more than one latch is connected to the output of each senseamplifier to allow the storing of multiple rows of data. This scheme isuseful for memory arrays in which the read time is much shorter than thewrite time. If several latches are present, a series of read operationscan be conducted simultaneously with a single write operation.

The invention encompasses other embodiments of a method, a system, andan apparatus, which are configured as set forth above and with otherfeatures and alternatives.

BRIEF DESCRIPTION OF THE DRAWINGS

For the present invention to be clearly understood and readilypracticed, the present invention will be described in conjunction withthe following figures, wherein like reference characters designate thesame or similar elements, which figures are incorporated into andconstitute a part of the specification, wherein:

FIG. 1A is a circuit diagram of a memory circuit, in accordance with afirst embodiment of the present invention;

FIG. 1B shows waveforms that illustrate the function of the data latchbetween the sense amplifier and the write data line of the circuit ofFIG. 1A, in accordance with a first embodiment of the present invention;

FIG. 1C shows other waveforms that illustrate the function of the datalatch between the sense amplifier and the write data line of the circuitof FIG. 1A, in accordance with a first embodiment of the presentinvention;

FIG. 2A is a circuit diagram of an exemplary gain cell structure used asthe memory element, in accordance with an embodiment of the presentinvention;

FIG. 2B shows waveforms that illustrate the function of the circuit ofFIG. 2A, in accordance with an embodiment of the present invention;

FIG. 2C is a cross-sectional diagram of a three-transistor cellemploying a thin-channel polysilicon transistor as the write transistorQW that can possibly be represented by the circuit shown in FIG. 2A, inaccordance with an embodiment of the present invention;

FIG. 3 is the a part of 3T memory cells written in JP10-1234565.

FIG. 4 is the array block diagram illustrating the peripheral circuitblocks and signals, in accordance with a first embodiment of the presentinvention;

FIG. 5 is the waveform diagram showing the access signals used for thecircuit in FIG. 4, in accordance with a first embodiment of the presentinvention;

FIG. 6A shows a circuit configured to generate the consecutive accesssignal CA of the first embodiment of the present invention;

FIG. 6B is the waveform for the circuit of FIG. 6A, in accordance with afirst embodiment of the present invention;

FIG. 7 is a circuit diagram for the word line signal generator, inaccordance with a first embodiment of the present invention;

FIG. 8 is the waveform diagram showing the access signals for thecircuit in FIG. 7, in accordance with a first embodiment of the presentinvention;

FIG. 9A is a circuit diagram for the column selector generator, inaccordance with a first embodiment of the present invention;

FIG. 9B is a waveform for the block diagram of FIG. 9A, in accordancewith a first embodiment of the present invention;

FIG. 10A is an array block diagram of the memory, in accordance with asecond embodiment of the present invention;

FIG. 10B is an exemplary waveform of the block diagram of FIG. 10A, inaccordance with a second embodiment of the present invention;

FIG. 11A is an array block diagram of peripheral circuit blocks andsignals of the memory, in accordance with a third embodiment of thepresent invention; and

FIG. 11B is a waveform diagram of the array block diagram of FIG. 11A,in accordance with a third embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

An invention for a high capacity, fast access dynamic random accessmemory is disclosed. Numerous specific details are set forth in order toprovide a thorough understanding of the present invention. It will beunderstood, however, to one skilled in the art, that the presentinvention may be practiced with other specific details.

FIG. 1A is a circuit diagram of a memory circuit, in accordance with afirst embodiment of the present invention. The block consists of a matMAT of memory cells arranged in columns and rows and a single memorycell MC is accessed by a read word line RWL, a write word line WWL, aread data line RDL, and a write data line WDL. A sense amplifier SAdiscriminates the data on the read data line by comparing the signalwith a reference signal VR. The output SO of the sense amplifier isconnected to the input of a latch element LT. In addition, input dataline DIN for the column is also connected to the input of the latchelement through a switch element. The output of the latch is connectedto the write data line WDL through a switch and presents the write datato the accessed cell. Furthermore, the output of the latch is connectedto the data out line DOUT through a buffer used to output read data tothe microprocessor.

Before the access characteristics of this memory architecture arepresented, a brief discussion of a dual data line destructive-write gaincell is beneficial. The three-transistor (3T) dynamic memory cell is anexample of a gain cell memory.

FIG. 2A is a circuit diagram of this three-transistor (3T) dynamicmemory cell used as the memory element, in accordance with an embodimentof the present invention.

FIG. 2B shows waveforms that illustrate the function of the circuit ofFIG. 2A, in accordance with an embodiment of the present invention. Asshown in FIG. 2A, a write transistor QW transfers charge from the writedata line WDL to the gate of the storage transistor QS when the writeword line WWL is raised to a high voltage level VDD. This stored chargeaffects the conduction of the storage transistor QS. Though in this casethe high voltage level of the write word line WWL is VDD, it is betterto set the write word line WWL to a voltage higher than VDD to write tothe storage node a voltage high enough that it is not effected by thethreshold of the write transistor. And there is case that the leakagecurrent reduces and a retention time gets longer if the low voltagelevel of write word line WWL is lower than OV. The value of the data isread by activating the read transistor QR by raising the read word lineRWL to a high voltage level VDD. During the activation, current willflow through the read QR and storage QS transistors from the read dataline RDL depending on the stored charge on the gate of the storagetransistor QS. A sense amplifier connected to the read data line RDL canthen determine the data of the cell depending on the level of currentfrom the read data line RDL. A low stored charge on the gate of thestorage transistor QS causes a high voltage read signal on the read dataline RDL. Conversely, a high stored charge causes a low voltage readsignal.

FIG. 2C is a cross-sectional diagram of a three-transistor cellemploying a thin-channel polysilicon transistor as the write transistorQW that can possibly be represented by the circuit shown in FIG. 2A, inaccordance with an embodiment of the present invention. A characteristicof some three transistor memory cells that utilize bulk CMOS transistorsis a relatively short data retention rate. The storage capacitance ofthe storage transistor QS gate is typically lower than that of a 1T-1Ccell. The charge leakage of the storage charge through the writetransistor QW can lead to loss of data at an unacceptably high rate. Onesolution is to use a thin-channel polysilicon transistor as the writetransistor QW. The drain, gate, and channel CH regions of the writetransistor QW can be formed from separate polysilicon layers. The sourceregion can be formed from the storage transistor QS gate polysilicon.Consider a case in which the channel CH is very thin, for example, lessthan or equal to 8 nanometers. In such a case, the storage chargeleakage in the off state can be drastically reduced versus that of abulk transistor, possible up to four orders of magnitude of reduction.If the channel CH is about 2 nanometers, the leakage current can bereduced to −19th power of 10. By using this type of polysilicontransistor, the data retention time may be increased, leading to a lowpower three transistor memory cell. For further description of theproperties and manufacturing process of this transistor, see U.S. patentapplication Ser. No. 10/167754.

The write access method for the first embodiment of the presentinvention can now be adequately described through the waveform diagramsshown in FIGS. 1B and 1C.

FIG. 1B shows waveforms that illustrate the function of the data latchbetween the sense amplifier and the write data line of the circuit ofFIG. 1A, in accordance with the first embodiment of the presentinvention.

FIG. 1C shows other waveforms that illustrate the function of the datalatch between the sense amplifier and the write data line of the circuitof FIG. 1A, in accordance with the first embodiment of the presentinvention. A high value write-cycle for an unselected column is shown inFIG. 1B. A corresponding low value write-cycle is shown in FIG. 1C.Similar to the latch-free method, a write cycle consists of a readphase, denoted by the activation of the read word line RWL, and a writephase, denoted by the activation of the write word line WWL. Also, thenegative voltage differential on the read data line RDL develops as inthe latch-free case. However, in this embodiment once a signal is fullyat the output of the sense amplifier SO, the signal is stored in thelatch LT on activation of the latch enable signal LE. At this point, thesignal develops from the output of the latch to the write data line WDLthrough a switch element. The write phase is performed by the activationof the write word line WWL and the transfer of charge from the writedata line WDL to the storage element in the memory cell MC. The writeaccess waveform for a low data value in a non-selected column is shownin FIG. 1C. This access proceeds similarly to the high data valueaccess. The difference is that during the read phase the voltage of theread data line RDL maintains a high value VDD due to the low conductionof the memory cell MC. When the sense amplifier SA is activated, a lowvoltage signal (0 V) develops at the sense amplifier output SO in orderto be written back to the memory cell MC. This signal is similarlystored in the latch element LT on activation of the latch enable signalLE. This in turn sets the signal on the write data line WDL to a lowvalue. The write phase follows accordingly in which the charge istransferred from the low value write data line WDL to the memory cellelement MC on activation of the write word line WWL.

The pipeline write operation for the first embodiment can besufficiently described by the circuit diagram of FIG. 4 and the waveformdiagram of FIG. 5.

FIG. 4 shows a diagram of a single memory bank, of which there may benumerous instances, in a cache memory, in accordance with the firstembodiment of the present invention. The individual memory cells MC areorganized into rows and columns as shown in FIG. 1 and described above.Precharge transistors QP are also shown in FIG. 4 for the sake ofcompleteness. A row decoder circuit XDEC and word line driver circuitsXDRV are used to determine the accessed row from the row address XADRand drive the appropriate word lines. Similarly, a column decoder YDECand a driver circuit YDRV are used to determine the block of columnsthat will be accessed during the read and write operations. Thesecircuits in turn drive the column read and write select transistors viathe data in select signal DIS and data out select signal DOS to connectthe selected columns to the data in lines DI and data out lines DO. Inaddition, a clock generator block CLK GEN creates the periodic signalsused throughout the array block and are determined by the read RD, writeWR, and clock CLK external inputs. An address control circuit ADR CTL isalso needed to generate a consecutive access signal CA that indicates aconsecutive access to the same row as described in more detail below.

FIG. 5 is the waveform diagram showing the access signals used for thecircuit in FIG. 4, in accordance with the first embodiment of thepresent invention. The waveforms provide further insight into theoperation of the pipeline write access of the first embodiment. Forexplanatory purposes, FIG. 5 shows two consecutive write accesses fortwo distinct row addresses on the same column. The first write accessbegins with the introduction of the address value A to the memory bankaddress input ADR and the activation of the external write signal WE attime T1. After the address has been decoded, the selected read word lineRWL1 is activated and the cell signals begin to develop on the columnread data lines as described previously. After a sufficient time, thesense amplifier is activated and the row data A is presented at thesense amplifier output SAMP. Simultaneously, external input data DI ispresented to the selected column bank via activation of the columnselect so that the new data overwrites the previously stored data. Attime T2, the latch enable signals LE are activated and the data isstored in the latches (LT DATA). This concludes the read phase of thefirst write access.

The pipeline operation of the write phase of the first access and theread phase of the second access can now be illustrated. The write datais presented to the write data lines WDL by the activation of the dataline select signal DLSW. After the signals on the write data line WDLare fully developed, the write word line WWL1 is activated and the cellcontents begin to be written. Simultaneously with the write phase of thefirst row access, the read phase of the second row access begins. Thesecond row address B is presented to the address decoder and the writesignal WE is asserted at time T3. Following the row address decoding,the read word line RWL2 is activated and the signal for the secondselected row begins to develop on the read data lines RDL. After theread signal fully develops on the read data line RDL, the senseamplifier is activated and the row data B is presented to the output ofthe sense amplifier SAMP. During this time, the write phase of the firstwrite access will be completed and the first write word line WWL1 andwrite data line select signal DLSW are deactivated. Following this, thesense amplifier data and the new data from the external input data busDI are stored in the latches by activation of the latch enable signal LEat time T4 and the pre-read phase of the second write operation ends.Following this, the normal write phase proceeds with the activation ofthe data line select signal DLSW, the activation of the second row writeword line WWL2, and the storing of the new data into the selected memorycells. As described here, the write phase and the read phase ofsubsequent row accesses are overlapped, or pipelined. A high-speedaccess is achieved by beginning the second access before the firstaccess is completed.

Two key features are necessary in a memory block to permit the pipelineaccess method. The first is that each column has a separate read dataline and write data line. This allows distinct values to be set for theread and write data lines during the overlapped-read and write phase ofthe consecutive accesses. Second, a method must be used that allows thewrite word line of one row to be activated at the same time as the readword line of another. One solution is to provide for two separate wordline decoder circuits, one for the read word lines and one for the writeword lines. However, a more compact solution is to use the same decoderfor both the read and write word lines. Accordingly, in the presentinvention, a latch is used to hold the decoded write word lineactivation signal while the subsequent read word line activation signalis being decoded. This method will be explained in further detail below.

The pipeline access presented in the first embodiment allows a reducedwrite access cycle time to the external signals with no cache miss orwait states. Consecutive read and write access can proceed indefinitelyas described above. However, special attention should be given toconsecutive accesses to the same row in the memory bank. For example,consider the case of a write then read access of the same row.Preferably, a read phase occurs for the first write access and the datais stored in the latch. Following this, the data is written to the cellwhile the next row is read simultaneously. For a consecutive access ofthe same row, after the read phase, the most current data is in thelatches since new data was introduced from the external data bus.Therefore, instead of reading the data from the row of cells, data mustbe read from the latches. For this reason, a signal must be madeavailable in order to indicate whenever a consecutive access is made tothe same row.

FIG. 6A shows a circuit configured to generate the consecutive accesssignal CA, in accordance with the first embodiment of the presentinvention.

FIG. 6B is the waveform for the circuit of FIG. 6A, in accordance withthe first embodiment of the present invention. As shown in FIG. 6A andFIG. 6B, only the row address lines XADR are necessary to generate thesignal. These address lines are input into a latch CLT and a comparatorCMP. The latch CLT and comparator CMP are clocked by an externalconsecutive access clock signal CACK. The function of the latch CLT isto hold the value of the row address XALT of the previous cycle to becompared to the row address XALT of the current access cycle. As shownin the waveform diagram, the first row address XADR A is compared to theprevious address on the rising edge of the clock signal CACK, resultingin a low signal. The falling edge of the clock signal CACK stores theaddress XADR in the latch CLT. On the following access, the identicalrow address is input and the rising edge of the clock signal CACKtriggers the comparator to generate a high consecutive access signal CA.This indicates a consecutive access and the other circuits in the memoryblock respond accordingly as will be described below. As illustrated inthe waveform diagram, when a non-consecutive access occurs XADR B, therising edge triggers the comparator to evaluate the input row addressXADR B and the latched row address XADR A, resulting in the output of alow signal. In this manner, the consecutive access signal CA is activeonly for a consecutive access of the same row.

FIG. 7 shows a row address decoder and word line signal circuit, inaccordance with the first embodiment of the present invention.

FIG. 8 is the waveform for the circuit of FIG. 7, in accordance with thefirst embodiment of the present invention. The circuit diagram in FIG. 7shows the row address lines XADR as inputs to a standard row decoderXDEC. The activated output signal from the row decoder XDEC is used togenerate the individual read word line signals RWL and is input into alatch WLT at each row. The stored signal in the latch WLT is used todrive the write word line signal WWL for that row on the write phase ofa write access. The additional circuitry in the bottom of FIG. 7 is usedto determine when the decoded row read lines RWL and write word linesWWL are to be enabled. The external read enable RE and write enable WEsignals determine whether the current access is a read or write. Theconsecutive access signal CA determines whether the access is for thesame row as the previous cycle and the generation circuit was describedabove. In addition, a set-reset latch SRL is used to hold the externalwrite signal WE value. The read clock RCK and write clock WCK signalsare input from the clock generation circuit and these periodic clocksignals are used to activate the enable signals based on the inputlogic.

The operation of the word line enabling circuitry of FIG. 7 can bedescribed along with an examination of the waveform diagram in FIG. 8.In FIG. 8, an exemplary access is shown which illustrates thefunctionality of the circuits in FIG. 7. A write-read-write three-cycleconsecutive access is performed on the same row address XADR A followedby a read access to a second row address XADR B and a write access to athird row address XADR C. On the first access, the row address XADR ispresented to the decoder XDEC and the external write signal WE isasserted. Since the consecutive access signal CA is low since this isthe first access, an assertion of the read clock RCK generates a highvalue of the read enable RE and the appropriate read word line RWL1 isdriven high. The read cycle completes with the amplification of the readdata line signal and the read data is stored in the column latch. Atthis point, the latch enable LTE is asserted and the set-reset latch SRLis triggered to store a high signal denoting a write access. The nextaccess is a read access to the same row. Since the data is in the columnlatches and not in the cell array, the circuit must delay the writephase of the first access and not enable the read word line RWL1. Thisis accomplished by a logic-AND function of the read RE and write WEsignals with the inverse of the CA signal. In other words, read wordline RWL1 and write word line WWL1 activations are disabled onsubsequent accesses to the same row. The column readout circuitrydescribed below will illustrate that the data is read from the columnlatches and not the cell array. The third access is a write to the samerow address XADR A. Again, since the CA signal is asserted, the readword line RWL1 and write word line WWL1 are disabled and the data iswritten directly into the column latches. On the fourth access, the rowaddress XADR changes and the consecutive access signal CA isdeactivated. Since a high value is stored in the set-reset latch SRL,the circuit has recorded that a write access has occurred and the datain the column latches must be written into the memory array. As thewrite enable clock WCK is activated, the write word line WWL1 of thefirst row activates and begins the write phase of the third access.Simultaneously, the row address XADR B for the read phase of the fourthaccess is decoded and the read word line RWL2 is activated. The fifthcycle is a read access to the third address XADR C and begins with theassertion of the external read signal RE. The write phase of theprevious write cycle begins with the activation of the write enableclock WCK and the write word line WWL2 of the second row is asserted.Simultaneously, on the rising edge of the read enable clock RCK, theread word line RWL3 of the third row is activated and the final readaccess is completed. This example illustrates how the minimal circuitryof FIG. 7 uses latches at each row to reduce the number of addressdecoders from two to one. In addition, this circuitry maintains theintegrity of the data even when the current data is stored in the columnlatches by only accessing the memory array when the consecutive accessesare to distinct rows.

FIG. 9A is an example of the column access circuitry, another importantelement of the first embodiment of the present invention.

FIG. 9B is the waveform diagram for the circuitry of FIG. 9A, inaccordance with the first embodiment of the present invention. Withreference to FIG. 9A and FIG. 9B, the functionality necessary topreserve the array data is described. Considering consecutive writeaccesses to the same row, it is necessary to read all of the data in therow to the column latches on the first access. However, on subsequentaccesses, since the data in the latch is valid and not the data in thecell array, subsequent writes should be performed only on those latchesin the array that receive new data from the external input data bus.This column circuitry controls the latch access through a combination ofthe decoded column address signals Y1-Yk, the external write enablesignal WE, the consecutive access signal CA and the latch clock LCK.

As shown in the diagram in FIG. 9A, the latch signal LE is triggered fora positive write enable WE and latch clock LCK under two conditions: (1)any access that is not a consecutive row access (CA is false) or (2) theset of columns is decoded (Y is high). The first case occurs for thefirst write access of a row. In this case, all of the data in the rowmust be stored in the column latches so that the correct data ispresented during the write phase of the write cycle. Since it is not aconsecutive access, the consecutive access signal CA is low and thewrite enable WE and latch clock LCK signals trigger all of the latchesat the appropriate time by the latch enable signal LE. In the secondcase, a consecutive row is written to and therefore the most currentdata for the row is stored in the latches. Only the new data is readfrom the external data bus and written to the latches of the selectedcolumn group. The column group is selected by the column decode signals(Y1˜Yk) and only the latch enable LE signal for the selected columngroup is activated during a consecutive write access.

A second embodiment of the present invention presents a structuresimilar to the first embodiment in which two separate memory mats sharea single sense amplifier SA and latch circuit LT.

FIG. 10A shows the circuit diagram of a pair of array columns and thecommon sense amplifier and latch circuits, in accordance with the secondembodiment of the present invention.

FIG. 10B shows exemplary access waveforms for the circuitry of FIG. 10A,in accordance with the second embodiment of the present invention. Inthe second embodiment, the memory is composed of a set of upper memorymats UMAT and lower memory mats LMAT. The cells are controlled by rowsignals including the read word lines URWL, LRWL UWRL, LWRL and thewrite word lines UWWL, LWWL. In addition, the mats are divided intocolumns of cells that are accessed through read data lines URDL, LRDLand write data lines UWDL, LWDL. In this embodiment, the upper read dataline URDL and lower write data line LRDL are connected to a single senseamplifier SA circuit. The output of the sense amplifier SA is thenconnected to the input of the latch element LT that is controlled by thecolumn latch signal LTI. The output of the latch can be connected toeither the upper write data line UWDL or the lower write data line LWDLthrough a corresponding switch element, which are independentlycontrolled by the upper latch output ULO and lower latch output LLOcolumn signals. The advantage of this structure is that the number andarea of peripheral circuits to the array. mats can be reduced by sharingthe sense amplifier and latch elements between a pair of mats. In thisembodiment, the total area of the circuitry can be reduced versus thefirst embodiment.

Another aspect of this embodiment is the use of a dummy cell structureto determine the reference signal in the sense amplifier as opposed to afixed voltage reference as presented in the previous embodiment. In FIG.10A, a dummy cell DC is located in each column of the upper memory matUMAT and the lower memory mat LMAT. The output of the dummy cell DC isconnected to the corresponding read data line URDL, LRDL and an outputis generated for the upper and lower dummy cells are accessed by theupper dummy access line UDL and lower dummy access line LDL,respectively. The function of the dummy cell DC is to generate areference signal for the sense amplifier when a row of data from theopposed memory mat is being read. When the upper memory mat UMAT isread, for example when URWL1 is accessed, then the lower dummy cell isaccessed by the lower dummy access line LDL. In this manner, the datasignal from the upper memory mat can be compared with the referencesignal generated by the dummy cell. Therefore, additional referencesignals, such as a fixed voltage reference as in the previousembodiment, are not necessary.

The signals and circuitry required to control the operation of thismemory structure can be explained along with the examination of theexemplary waveform diagrams presented in FIG. 10B. In this diagram, awrite operation to the upper array mat and a subsequent write operationto the lower array mat is described. The first write access begins withthe presentation of an address A and the assertion of the write enablesignal WE beginning at time T1. In this example, it is assumed that thefirst access is a row in the upper memory mat UMAT activated by the readand write word lines URWL1 and UWWL1. After the address is decoded, theupper read word line URWL1 for the decoded row is asserted.Simultaneously, the dummy cell in the lower mat LMAT column is activatedby LDL. After a sufficient time, the sense amplifier SA is activated andthe row data A develops at the output of the sense amplifier SAMP. Thisdata is latched into the latch circuit LT by the latch input columnsignal LTI1 at time T2. The write phase to rewrite the old data isinitiated by the assertion of the upper latch output signal ULO1 atwhich point the write data is presented to the upper write data lineUWDL. The contents are written back to the cell with the assertion ofthe selected row write word line UWWL1. As the contents are written tothe cell, the following write cycle begins. The next row address B ispresented to the array and the write enable signal WE is asserted attime T3. In this example, it is assumed that this write cycle is for arow in the lower memory mat LMAT. When the row address is decoded, theread word line LRW1 is asserted and the contents of the cell are outputto the lower read data line LRDL. After the data line signal issufficiently developed, the sense amplifier is activated and the rowdata B are presented to the sense amplifier output SAMP. At this point,the write cycle of the previous access is completed by the deactivationof the upper write word line UWWL1. The row data at the sense amplifieris stored in the latch by the activation of the latch input signal LTI1at time T4. Following this phase, the write phase of the second accesscompletes in a similar manner to the first access. In this manner, theread and write phases of two consecutive cycles have been overlapped andthe effective cycle time is shortened. The shared configurationpresented in this embodiment allows for a smaller area occupation of theperipheral circuit and leads to an overall decrease in manufacturingcosts.

A third embodiment of the present invention concerns memory arrays inwhich the read phase is much shorter than the write phase of the writecycle.

FIG. 11A shows the circuit diagram of a single array column, inaccordance with the third embodiment of the present invention.

FIG. 11B shows exemplary access waveforms for the circuitry of FIG. 11A,in accordance with the third embodiment of the present invention. Afundamental difference here from the first embodiment is that severallatches are placed between the sense amplifier SA and the write dataline WDL instead of a single latch. With this configuration, theeffective write access speed of the memory array can be increased versusthat in the first embodiment. For a write phase that is several timesslower than the read phase, the access speed of the first embodiment islimited to the speed of the write phase. In this embodiment, theeffective access speed is limited to the speed of the faster read phase.

An analysis of the circuit diagram and exemplary waveforms will aid inthe explanation of this embodiment's functionality. As shown in FIG.11A, the memory array is similar to that of the first embodiment with aseries of memory cells arranged in rows and columns. Each memory cell isconnected to a read word line RWL, a write word line WWL, a read dataline RDL and write data line WDL. Each read data line RDL is connectedto a sense amplifier SA to determine the data value. The output of thesense amplifier SA is connected to the input of two or more latchcircuits LT. In addition, the external data input DIN is connected tothe inputs of the latch elements LT through a switch enabled by the datainput switch signal DIS. The input latch activation of each latchelement LT is activated by a unique latch input signal (LTI1˜LTIp). Theoutput of each latch element LT is connected to the write data line WDLthrough a switch activated by a unique latch output enable signal(LTO1˜LTOp). Finally, the value of the write data line can be output tothe external output data bus DOUT through a switch activated by the dataoutput signal DOS.

The functionality of the circuit of the second embodiment can bedescribed along with the waveforms of FIG. 10B. Since there are severallatches LT per column, multiple row data can be stored simultaneously.In the case of a write access for a fast read phase and slow write phasememory array, several rows can be quickly read and stored in the columnlatches LT. In principle, multiple read phases occur while a singlewrite phase is executed. Therefore, the system bus does not have to waitfor the completion of the write phases to perform the read phases andcontinue on the access other memory arrays. In the exemplary waveform,two write accesses are performed sequentially for two distinct rowaddresses XADR A and XADR B. After the address is decoded for the firstrow address XADR A, the data is read and stored in the first latch LT bythe activation of the first input latch signal LTI1. At this point, thewrite phase of the cycle occurs by activation of the latch output switchsignal LTO1 and the activation of the write word line WWL1. The secondaccess address XADR B is then decoded and the data is developed at thesense amplifier output SAMP. Unlike the circuit in the first embodiment,this signal can be stored by activating the second input latch signalLTI2 even while the write phase of the first access is still occurring.If a third access XADR C occurs, this data can also be read while thefirst write phase is occurring, as shown in the lower part of thediagram. In this manner, the array access time is limited to the time ofthe read phase of the access, which can be much faster than the writephase for certain memories.

This scheme has two cases where the external access is longer than theread phase time. The first case is when the latches LT become full ofrow data and a write phase is not completed. For example, consider asystem with three column latches and a write phase three times longerthan the read phase. The first three write accesses will store the threerows of data in the available column latches. However, on the fourthaccess, the external bus must wait until the write phase of one of therows is completed and a latch is free. In summary, access speed islimited to the read phase speed for all access up until the latches arefull. All subsequent accesses are limited to the write phase speed untilan additional latch is freed. The second case is when a write access toa row occurs for a row that is currently in the write phase of a priorwrite access. In this case, since the write word line for the row isactivated, the external access must be suspended until the row data inthe array is updated. After the write word line is deactivated, the newexternal data can be read directly into the latch without executing aread phase from the array since the most current data is in the array.

In the foregoing specification, the invention has been described withreference to specific embodiments thereof. It will, however, be evidentthat various modifications and changes may be made thereto withoutdeparting from the broader spirit and scope of the invention. Thespecification and drawings are, accordingly, to be regarded in anillustrative rather than a restrictive sense.

1. A semiconductor device comprising; a memory array including aplurality of read word lines, a plurality of write word lines, a readbit line, a write bit line, and a plurality of memory cells coupled tothe read and write bit lines, wherein the semiconductor device operatesa write cycle to write data inputted from outside of the memory arrayinto the plurality of the memory cells, wherein in the write cycle, oneof the plurality of read word lines is activated to read data stored inone of the plurality of memory cells in a read phase and then one of theplurality of write word lines is activated to write data, which iscorresponding to the data inputted from outside of the memory array orthe read data in the read phase, in a write phase, wherein when one ofthe write word lines is activated in the write phase of a first writecycle, another one of the plurality of read word lines can be activatedin parallel to read data from another one of the plurality of the memorycells, which is different from selected memory cell in the write phaseof the first write cycle, in the read phase of a second write cycle nextto the first write cycle.
 2. The semiconductor device according to claim1, wherein each of the plurality of memory cells has a first transistorwhose source or drain is coupled to the read bit line and a secondtransistor whose source or drain is coupled to the write bit line. 3.The semiconductor device according to claim 2, wherein the secondtransistor is a thin-channel poly-silicon transistor having a channelregion thickness of 5 nanometers or less.
 4. The semiconductor deviceaccording to claim 2, wherein, each of the plurality of memory cellsfurther has a third transistor whose source and drain are coupledbetween another one of source or drain of the first transistor and afirst potential and whose gate is coupled to another one of source ordrain of the second transistor.
 5. The semiconductor device according toclaim 4, wherein the second transistor is a thin-channel poly-silicontransistor having a channel region thickness of 5 nanometers or less. 6.The semiconductor device according to claim 1, further comprising: afirst latch circuit coupled between the read bit line and the write bitline, wherein the first latch circuit hold data read out from one of theplurality of memory cells in the read phase.